MacroAgent Improves VLSI Design Regularity with LLM-Agent-Designed Algorithms

In modern Very Large-Scale Integration (VLSI) designs, macros are critical components, and their precise placement significantly influences the final quality of result (QoR). Macro legalization, the final step in determining macro positions, often faces challenges with existing approaches lacking robustness, incurring high computational costs, or failing to account for macro regularity. MacroAgent, a new four-stage framework, addresses these limitations. It involves clustering, contour generation, template matching, and inter-cluster refinement. A key innovation is the use of Large Language Models (LLMs) to discover multiple effective, heuristic, regularity-aware contour algorithms, enabling the framework to generate robust and efficient solutions for macro legalization. Experimental results on TILOS and Chipyard benchmarks demonstrate MacroAgent's superior performance, showing a 2 to 8-fold improvement in layout regularity and a 3% to 5% reduction in routed wirelength with comparable congestion after global routing. End-to-end evaluation with Cadence Innovus confirms these regularity improvements translate into tangible Power, Performance, and Area (PPA) gains, including 2.9% lower routed wirelength and a 68.3% TNS improvement over baseline methods.