DeepSeq3: Hierarchical Graph Learning for Scalable Circuit Analysis

Circuit Representation Learning (CRL) holds great promise for optimizing Electronic Design Automation (EDA) tasks, but its adoption is hampered by the massive scale of industrial netlists and the difficulty in modeling temporal dynamics at the register level. A new framework, DeepSeq3, aims to overcome these limitations by introducing a hierarchical approach. DeepSeq3 abstracts circuits into a two-level representation. At the fine-grained level, it partitions combinational subgraphs using flip-flops (FFs). At a higher level, it creates a Super-Node Graph (SNG) to model the register-transfer structure. A dual Graph Neural Network (GNN) architecture then learns representations for both levels, capturing both local Boolean logic and global state transitions. A crucial innovation is a state-centric pre-training scheme that predicts reachability between FF states, giving the model a deep understanding of temporal behavior. Demonstrated on large-scale benchmarks, DeepSeq3 shows superior scalability and richer representations, leading to an 18% reduction in bounded model checking (BMC) solving time while maintaining correctness.