SINA Automates Circuit Schematic to Netlist Conversion.

The field of Electronic Design Automation (EDA) is being transformed by AI, particularly with large language models (LLMs) assisting in circuit design. However, a significant hurdle remains: the vast amount of circuit design knowledge locked in visual formats like schematic images from research papers, textbooks, and websites. These images are not directly usable by EDA tools, making their conversion into machine-readable netlists essential for simulation, verification, and building AI-compatible databases. Current conversion methods often lack generalization across different types of schematics (Integrated Circuit and Printed Circuit Board) and struggle with accurate component recognition, connectivity inference, and distinguishing between connected junctions and crossing wires. This paper introduces SINA, an open-source, fully automated pipeline designed to convert circuit schematic images into netlists. SINA integrates several AI techniques to achieve its high performance. It employs deep learning for robust component detection, connected-component labeling for precise connectivity inference, Optical Character Recognition (OCR) for extracting component reference designators, and a Vision-Language Model (VLM) for reliably assigning these designators. A key feature of SINA is its ability to handle both IC- and PCB-level schematics and its dedicated crossing-wires detection mechanism, which accurately differentiates between wire intersections that are connected and those that merely cross. The correctness of the generated netlists is validated using graph isomorphism techniques. Experimental results demonstrate an impressive overall netlist generation accuracy of 96.67%, which is 2.72 times higher than state-of-the-art approaches, marking a significant advancement in automating circuit design workflows.