EXPLORE Boosts Analog Circuit Design with Guided LM Search

Automating the design of analog circuit topologies is a critical step towards reducing the extensive manual effort currently required to meet diverse application demands. While recent advancements have used fine-tuned language models (LMs) for direct, one-shot generation of circuit topologies from user specifications, these methods struggle with complex circuits due to vast search spaces and limited training data. This paper introduces EXPLORE, a novel framework designed to scale analog topology generation at test-time. EXPLORE combines simulator-guided Monte Carlo Tree Search (MCTS) with transformer-based decoding. This integration allows the system to leverage the prior knowledge embedded in language models while strategically allocating expensive simulator resources primarily to decisions that significantly alter the topology. On a challenging 6-component benchmark with tight tolerances, EXPLORE dramatically increased the success rate from 12% (one-shot generation) and 33% (sampling-and-filter baseline) to 65%. It also reduced the Mean Squared Error by over 20% compared to the sampling-and-filter method under the same search budget. These results position EXPLORE as a significant step towards practical, scalable LLM-driven automation in analog circuit design.