Latent Diffusion Models Improve Chip Routability Estimation.

This research introduces CLDRoute, a novel framework that redefines routability estimation in physical chip design as a conditional generation problem. Unlike previous methods that offered deterministic predictions of congestion or design rule checking (DRC) violations, CLDRoute utilizes conditional latent diffusion to model these as spatially structured routability fields. This approach allows for a more nuanced understanding of chip design challenges. CLDRoute incorporates physics-aware conditioning and task-specific latent modeling to effectively handle the distinct characteristics of congestion and DRC maps. A key advantage of this framework is its ability to perform sample-based inference, providing not only an expected outcome but also an estimate of spatial uncertainty for a given input design. Empirical results on the CircuitNet 2.0 dataset demonstrate CLDRoute's superior performance in generating both DRC violation and congestion maps, achieving high SSIM and low MAE scores. By offering both prediction and uncertainty, the framework provides a more practical and comprehensive view of routability during the critical placement stage of chip design.