ParasGB: New Benchmark Suite for AMS Circuit Parasitic Estimation

Jiajun Zou, Jiawei Liu, Ao Liu, Junnong Tian, Yibin Zhang, Chengjie Liu, Yuxi Wang, Shan Shen, Wenhua Gu, Jun Yang, Wenjian Yu· July 28, 2026 View original

Summary

ParasGB is the first open-source benchmark suite for pre-layout parasitic parameter prediction on circuit graphs, addressing the lack of high-fidelity RC benchmarks. It provides large-scale, heterogeneous RC networks from tape-out-proven designs, enabling reproducible research on GNN-based parasitic modeling.

A significant hurdle in the advancement of GNN-based parasitic modeling for analog and mixed-signal (AMS) circuits has been the absence of publicly available, high-fidelity RC benchmarks that support reproducible evaluation. To bridge this gap, researchers have introduced ParasGB, the first open-source benchmark suite specifically designed for pre-layout parasitic parameter prediction on circuit graphs. This suite aims to facilitate early-stage estimation of parasitic capacitance and resistance, which are increasingly critical for AMS circuit performance in deep submicron manufacturing processes, often leading to costly layout iterations. ParasGB offers a collection of large-scale, heterogeneous RC networks. These networks are extracted using commercial Electronic Design Automation (EDA) tools from actual tape-out-proven designs, ensuring their relevance and realism. The suite also includes a unified evaluation protocol that covers node-level ground capacitance, edge-level resistance, and edge-level coupling capacitance. Within this standardized framework, the developers have benchmarked various Graph Neural Network (GNN) architectures using a consistent training pipeline. This process has highlighted several challenges inherent in parasitic estimation, such as extreme label imbalance, long-tailed parasitic distributions, and strong structural heterogeneity. By providing a physically grounded and standardized benchmark, ParasGB creates an open platform for reproducible research in circuit graph learning and the development of parasitic-aware models, which is crucial for modern chip design.

Why it matters

For chip designers and EDA tool developers, ParasGB provides a crucial standardized benchmark to accelerate research and development of GNN-based tools for early and accurate parasitic estimation, reducing design iterations and time-to-market.

How to implement this in your domain

  1. 1Utilize ParasGB to benchmark and validate new GNN architectures for parasitic estimation in AMS circuits.
  2. 2Integrate ParasGB datasets into your research or development pipeline for training and testing parasitic-aware design tools.
  3. 3Contribute to the ParasGB community by sharing new models or insights gained from using the benchmark.
  4. 4Leverage the insights from ParasGB's challenges (e.g., label imbalance) to develop more robust GNN training strategies for circuit analysis.

Who benefits

SemiconductorElectronics ManufacturingEDA SoftwareAI Hardware

Key takeaways

  • ParasGB is the first open-source benchmark for parasitic estimation on AMS circuits.
  • It provides high-fidelity RC networks from tape-out-proven designs.
  • The suite enables reproducible research on GNN-based parasitic modeling.
  • It highlights challenges like label imbalance and structural heterogeneity in circuit graphs.

Original post by Jiajun Zou, Jiawei Liu, Ao Liu, Junnong Tian, Yibin Zhang, Chengjie Liu, Yuxi Wang, Shan Shen, Wenhua Gu, Jun Yang, Wenjian Yu

"arXiv:2607.23225v1 Announce Type: new Abstract: As chip manufacturing processes advance to deep submicron nodes, parasitic interconnect effects increasingly dominate the performance of analog and mixed-signal (AMS) circuits and often lead to costly layout iterations. This makes e…"

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Originally posted by Jiajun Zou, Jiawei Liu, Ao Liu, Junnong Tian, Yibin Zhang, Chengjie Liu, Yuxi Wang, Shan Shen, Wenhua Gu, Jun Yang, Wenjian Yu on X · view source

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