Self-Organizing Digital Circuits Enhance Fault Tolerance.

Traditional fault tolerance in computing relies on static methods like hardware redundancy or error-correcting codes. In contrast, biological systems exhibit remarkable adaptive plasticity, maintaining function by dynamically reorganizing around damage. Inspired by this biological principle, new research proposes "Self-Organising Digital Circuits." This innovative architecture frames the generation and maintenance of functional logic as a meta-learning problem on graphs. It employs a topology-masked Transformer to configure the Lookup Tables (LUTs) of a circuit's Boolean gates. Unlike Neural Cellular Automata (NCA) that regenerate a fixed target state, this system navigates the complex Boolean search space to fulfill a computational task. The circuits can self-assemble from scratch and rapidly re-route logic to bypass unforeseen permanent hardware faults. Furthermore, the system demonstrates near-perfect recovery from soft errors, even for damage sizes far exceeding its training conditions, and shows generalization across different circuit scales.