VeriTrace Achieves 100% Verilog RTL Generation Accuracy

Yu-Tung Liu, Cunxi Yu· August 5, 2026 View original

Key takeaways

  • Existing Verilog RTL generation agents are limited by incomplete debugging action spaces.
  • VeriTrace introduces "Agentic Temporal Exploration" for human-like debugging.
  • It allows independent control over signal selection, time windows, and iteration depth.
  • VeriTrace achieves 100% Pass@1 on VerilogEval-V2, a significant accuracy breakthrough.

Who benefits

SemiconductorElectronicsHardware DesignEDA (Electronic Design Automation)Aerospace

Summary

VeriTrace is a multi-agent system that achieves 100% accuracy on the VerilogEval-V2 benchmark for RTL generation by enabling human-like temporal exploration in its Inspector agent. This complete debugging action space allows for hypothesis-driven root-cause analysis, overcoming limitations of previous systems.

Current state-of-the-art multi-agent systems for automated Verilog RTL generation typically plateau at around 95% accuracy on standard benchmarks. This limitation stems from an incomplete debugging action space, where agents are restricted in their ability to inspect signals, query time windows, or both. This forces debugging into a pattern-matching approach rather than true hypothesis-driven root-cause analysis. VeriTrace, a new multi-agent system, addresses this by equipping its Inspector agent with a complete debugging action space. This "Agentic Temporal Exploration" allows independent control over signal selection, time-window bounds, and iteration depth, mimicking how human verification engineers explore and debug circuits. By enabling agents to form hypotheses, query waveforms for evidence, and iteratively refine their understanding, VeriTrace has achieved 100% Pass@1 on the VerilogEval-V2 benchmark, marking the first system to reach perfect functional correctness. Even with the same Claude Sonnet 4.0 backbone, VeriTrace significantly outperforms existing baselines, demonstrating the critical role of a comprehensive debugging agency.

Why it matters

For hardware engineers, chip designers, and AI developers in the semiconductor industry, VeriTrace represents a significant leap forward in automated RTL generation and verification, potentially accelerating design cycles and reducing costly errors.

How to implement this in your domain

  1. 1Evaluate VeriTrace's approach for improving automated Verilog RTL generation in chip design workflows.
  2. 2Explore integrating advanced debugging agents with complete action spaces into existing verification tools.
  3. 3Investigate how hypothesis-driven root-cause analysis can be automated for complex engineering problems.
  4. 4Consider the implications of achieving 100% functional correctness on benchmarks for future design automation.

Original post by Yu-Tung Liu, Cunxi Yu

"arXiv:2608.02878v1 Announce Type: new Abstract: Large language models have shown promise for automated Verilog RTL generation, yet state-of-the-art multi-agent systems plateau at ~95% accuracy on standard benchmarks. We trace this ceiling to an incomplete debugging action space:…"

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