EDATracer Framework Boosts Chip Design Analysis with LLM Agents

Modern chip design relies heavily on Electronic Design Automation (EDA) tools, which produce vast amounts of diverse data artifacts like source files, logs, and reports. Analyzing this data is crucial for debugging and optimizing chip designs, but it's challenging due to the distributed nature of relevant information across various artifact types and design stages. While large language model (LLM) agents show promise in assisting EDA, current approaches often lack public benchmarks for large-scale, cross-artifact analysis and struggle to ground their reasoning in actual tool-generated evidence. A new framework, EDATracer, addresses these limitations by providing an evidence-grounded approach to EDA artifact analysis. It organizes design artifacts into a knowledge graph, complemented by a semantic vector index, allowing LLM agents to efficiently retrieve and synthesize evidence from different sources. The researchers also developed an 18.9 GB dataset of open-source chip designs and a 90-question benchmark to evaluate the framework's performance. In evaluations, EDATracer demonstrated superior performance, achieving the best pass@1 accuracy among tested agents, outperforming commercial models like Cursor and Claude Code by 6.4 and 7.2 percentage points, respectively. Furthermore, it achieved these results with significantly fewer tokens, using 2.0-3.2 times less, highlighting its efficiency and effectiveness in complex EDA tasks.