LLMs Refine Analog IC Layouts with Simulation-Aware Policy

This paper introduces a novel simulation-aware multi-agent framework leveraging Large Language Models (LLMs) to refine analog integrated circuit (IC) layouts. Analog IC layout design is notoriously labor-intensive, requiring numerous simulation-driven iterations to meet stringent specifications, even after initial placement and routing by automated generators. Traditional Bayesian Optimization (BO) methods, while effective, demand hundreds to thousands of costly post-layout simulations, making them impractical. The proposed framework employs in-context policy improvement (ICPI), where LLMs iteratively update layout optimization parameters. This is achieved through an "act-observe-reflect" loop that interacts with an analog layout generator using compact structured layout representations. The LLMs gain simulation awareness, allowing them to make more informed decisions about parameter adjustments. Experiments on real-world analog circuits demonstrated the framework's efficiency. With only tens of post-layout simulations, the approach significantly improved post-layout performance, surpassing both the generator's built-in heuristics and BO-based tuning methods. This marks a substantial advancement in accelerating the analog IC design process.