PPAPlace Optimizes Chip Placement for Better Performance

This research presents PPAPlace, a novel approach to chip placement optimization that directly addresses the limitations of traditional methods. Conventional placement algorithms primarily optimize for half-perimeter wirelength (HPWL), which has been shown to have a near-zero correlation with critical post-route timing metrics like worst negative slack (WNS) and total negative slack (TNS). This disconnect often leads to AI placers degrading overall PPA (Performance, Power, Area) compared to hierarchical baselines. PPAPlace introduces a timing-driven differentiable surrogate model capable of predicting post-route PPA directly from both macro and standard-cell placements. This dual-stream predictor combines graph attention over the chip netlist with spatial convolution over the placement grid. Crucially, it is trained on post-global-routing labels, which a fidelity study identified as the best balance between final timing accuracy and label generation cost. The gradients from PPAPlace's predicted WNS and TNS flow end-to-end back to cell coordinates. These gradients are then exploited in two ways: either as a co-objective within an analytical placer's optimization loop (PPAPlace-CoOpt) or as a post-placement refinement step using projected gradient descent (PPAPlace-Refine). On unseen test circuits, PPAPlace demonstrated substantial improvements in average WNS (22%) and TNS (51%) over hierarchical baselines, while maintaining power and routability, without requiring retraining for new circuits.